This application relates to the operation of NAND flash memory systems, and, more specifically, to interfaces for communicating between NAND flash memory chips and NAND flash memory controllers in such systems.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retains its stored data even after power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory, both embedded and in the form of a removable card is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions. In particular, flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.
One type of flash memory that has become particularly popular for mass data storage applications is NAND flash memory. NAND flash memory is cost-effective for mass data storage, where data is not being frequently replaced or updated. For example, USB thumb drives, and Solid State Disks (SSDs) often use NAND flash memory for mass data storage. NAND flash memory chips are generally considered as commodity products that may meet some standardized specifications and communicate through standardized interfaces (e.g. “Legacy” Asynchronous mode and “Toggle Mode” interfaces). In addition to memory cells connected in a NAND configuration, a NAND flash memory chip generally includes peripheral circuits and controller interface circuits that manage communication with a NAND flash memory controller.
A NAND flash memory controller is typically provided within a NAND flash memory system to perform a variety of functions that may include logical-to-physical address translation, Error Correction. Coding (ECC), bad-block management, management of multiple NAND flash memory chips, communication with a host system, and other functions. The NAND flash memory controller is located between the NAND flash memory and the host so that the host accesses the NAND flash memory through the controller. A NAND flash memory controller is typically formed as a dedicated chip, an Application Specific Integrated Circuit (ASIC) that is designed to perform the particular functions needed in a particular memory system. Alternatively, some sort of general purpose memory controller may be loaded with firmware that is specific to a particular application. In either case, a NAND flash memory controller chip, separate from the NAND flash memory chip, or chips, is provided and connected between the NAND flash memory and the host.
NAND flash memory systems communicate with host systems over a variety of different interfaces such as USB, Compact Flash (CF), Secure Digital (SD), etc., which allow memory systems to be easily removed from one host and subsequently connected to another host that has an appropriate interface. In contrast, NAND flash memory controller chips and NAND flash memory chips are generally hard-wired to each other (bonded together within the same package, or on the same PCB) and are not configured to be removable. Typically, they are connected together using a simple parallel interface to allow high-speed data transfer. However, such simple parallel interfaces are not ideal for all NAND flash memory systems.